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PROJECT BRIEF
ON 
COMPOSITE UNIT FOR APPLICATION SPECIFIC INTEGRATED CIRCUITS (ASICs)
(Using Base Array Wafer)

1. Product: ASICs

2. Capacity: 25 Million Nos.Chips per year

3. Technology: Technology will have to be imported. Assistance of Central Electronics Engineering Research Institute (CEERI), Pilani could be sought.

4. Process: The following three major steps are involved in the process:-

a) Mask Generation for base array wafer.
b) Processing of wafer viz. chemical vapour deposition, photo lithography & metallisation.
c) IC packaging- Thinning, scribing & breaking, die bonding, wire bonding, lid sealing for ceramic pagkages or plastic 
packages.

5. Market: The demand (Rs.in million) for ICs are as under :-

Also the range of ICs required is large,which does not produce economics of scale, therefore the ASICs hold a very good promise. The projected market in India is approx.Rs.180.0 crores annually.

6. Land & Building: About 5000 Sq. Mtrs. constructed area on 20000 Sq. Mtrs. land.

7. Major Plant & Machinery: Beam Mask making, Mask Inspection & repair, Metal etcher, Wafer stepper, spinner Wafer track stepper interface, Asher/Barrel Etcher, Passivation PECVD, Nitride etch, chemical work station, Microscope even, UPS, IC Wafer probe, Die inker, IC tester, Probe card, Building equipment., Dicing saw, wire bonder, moulding press etc. 

8. Raw Material: Base Array Wafer to be imported.

9. Estimated project Cost: Rs. 125.00 Crores.

10. Tentative means of finance:

11. Manpower:

 12. Utilities:

13. Estimated Turnover: 200 crores

14. Estimated pay back period: 6 years.